ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 119

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.24 XAH_CTRL_1 – Transceiver Acknowledgment Frame Control Register 1
8266A-MCU Wireless-12/09
This register controls the sensitivity threshold of the receiver.
• Bit 7 – RX_PDT_DIS - Prevent Frame Reception
RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in
receive modes. An ongoing frame reception is not affected. This operation mode is
independent of the setting of register bits RX_PDT_LEVEL.
• Bit 6:4 – Res2:0 - Reserved
• Bit 3:0 – RX_PDT_LEVEL3:0 - Reduce Receiver Sensitivity
These register bits reduce the receiver sensitivity such that frames with a RSSI level
below the RX_PDT_LEVEL threshold level are not received (RX_PDT_LEVEL>0). The
threshold level can be calculated according to the following formula: RX_THRES >
RSSI_BASE_VAL+3·(RX_PDT_LEVEL-1), for RX_PDT_LEVEL>0. If register bits
RX_PDT_LEVEL>0 the current consumption of the receiver in states RX_ON and
RX_AACK_ON is reduced by 500 µA. If register bits RX_PDT_LEVEL=0 (reset value)
all frames with a valid SHR and PHR are received, independently of their signal
strength. Examples for certain register settings are given in the following table.
Table 9-60 RX_PDT_LEVEL Register Bits
This register is a multi-purpose control register for various RX_AACK settings.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 5 – AACK_FLTR_RES_FT - Filter Reserved Frames
This
AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as
Bit
NA ($157)
Read/Write
Initial Value
Bit
NA ($157)
Read/Write
Initial Value
Register Bits
RX_PDT_LEVEL3:0
register
Res1
R
Res
7
0
R
bit
3
0
shall
AACK_ACK_TIME AACK_PROM_MODE
Res0
R
6
0
only
RW
2
0
Value
0xE
0xF
AACK_FLTR_RES_FT AACK_UPLD_RES_FT
0x0
0x1
0x2
be
set
RW
5
0
Description
RX_THRES
value); RSSI value not considered
RX_THRES > RSSI_BASE_VAL + 0 · 3;
RSSI > -90 dBm
...
RX_THRES > RSSI_BASE_VAL + 13 · 3;
RSSI > -51 dBm
RX_THRES > RSSI_BASE_VAL + 14 · 3;
RSSI > -48 dBm
RW
if
1
0
AACK_UPLD_RES_FT
ATmega128RFA1
RSSI_BASE_VAL (Reset
RW
4
0
Res
R
0
0
XAH_CTRL_1
XAH_CTRL_1
=
1.
119
If