ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 476

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.7.15 Parallel Programming Characteristics
476
ATmega128RFA1
Figure 31-10. Parallel programming timing including some general timing requirements
Figure 31-11. Parallel programming loading sequence with timing requirements
Note:
Figure 31-12. Parallel programming reading sequence (within the same page) with
timing requirements
Note:
(DATA, XA0/1, BS1, BS2)
PAGEL
DATA
CLKI
DATA
CLKI
BS1
XA0
XA1
BS1
XA0
XA1
OE
Data & Control
1. The timing requirements shown in
1. The timing requirements shown in
RDY/BSY
also apply to loading operation.
also apply to reading operation.
PAGEL
ADDR0 (Low Byte)
ADDR0 (Low Byte)
LOAD ADDRESS
CLKI
LOAD ADDRESS
WR
(LOW BYTE)
(LOW BYTE)
(1)
t
XLOL
t
t
BVPH
DVXH
t
OLDV
t
t
XHXL
PHPL
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
t
t
t
READ DATA
(LOW BYTE)
DATA (Low Byte)
t
XLWL
XLDX
PLBX
PLWL
t
XLXH
t
BVWL
Figure 31-10 above
Figure 31-10 above
t
BVDV
t
(HIGH BYTE)
WLWH
LOAD DATA
WLRL
DATA (High Byte)
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
XLPH
LOAD DATA
t
WLBX
(i.e., t
(i.e., t
t
OHDZ
t
PLXH
DVXH
DVXH
8266A-MCU Wireless-12/09
t
WLRH
LOAD ADDRESS
, t
, t
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
XHXL
XHXL
ADDR1 (Low Byte)
ADDR1 (Low Byte)
, and t
, and t
(1)
XLDX
XLDX
)
)