ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 55

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.2.4.1 RX_AACK Slotted Operation – Slotted Acknowledgement
8266A-MCU Wireless-12/09
2. At least one address field must be configured.
Address match, indicated by the TRX24_AMI interrupt is further controlled by the
content of subfields of the frame control field of a received frame according to the
following rule:
If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no
TRX24_AMI interrupt is generated, refer to
causes all acknowledgement frames not to be announced which otherwise always pass
the filter regardless of whether they are intended for this device or not.
For backward compatibility to IEEE 802.15.4-2003 third level filter rule 2 (Frame
Version) can be disabled by the bits AACK_FVN_MODE of register CSMA_SEED_1.
Frame filtering is available in Extended and Basic Operating Mode (see section
Operating Mode" on page
TRX24_AMI interrupt, if enabled.
The radio transceiver supports slotted acknowledgement operation according to
IEEE 802.15.4-2006, section 5.5.4.1.
In RX_AACK mode with bit SLOTTED_OPERATION of register XAH_CTRL_0 set, the
transmission of an acknowledgement frame has to be controlled by the microcontroller.
If an ACK frame has to be transmitted the radio transceiver expects writing SLPTR=1 to
actually start the transmission. This waiting state is signaled 6 symbol periods after the
reception of the last symbol of a data or MAC command frame by bits TRAC_STATUS
of register XAH_CTRL_0, which are set to SUCCESS_WAIT_FOR_ACK in that case. In
networks using slotted operation the start of the acknowledgment frame and thus the
exact timing must be provided by the microcontroller.
A timing example of an RX_AACK transaction with bit SLOTTED_OPERATION of
register XAH_CTRL_0 set is shown in the next figure. The acknowledgement frame is
ready to transmit 6 symbol times after the reception of the last symbol of a data or MAC
command frame. The transmission of the acknowledgement frame is initiated by the
microcontroller by writing SLPTR=1 and starts 16µs (t
t
IRQ
Note:
is specified in section
1. Filter
2. Filter rule 2 is affected by register bits AACK_FVN_MODE (see register
AACK_UPLD_RES_FT
Acknowledgment Frame Control Register 1" on page
"CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2" on
page
129).
rule
1
"Digital Interface Timing Characteristics" on page
is
35); a frame passing the frame filtering generates an
affected
(see
by
register
Figure 9-26 on page
register
ATmega128RFA1
"XAH_CTRL_1
bits
TR10
) later. The interrupt latency
119).
AACK_FLTR_RES_FT
63. This effectively
–
507.
Transceiver
"Basic
and
55