ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 278

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.11.17 TCCR3B – Timer/Counter3 Control Register B
278
ATmega128RFA1
• Bit 7 – ICNC3 - Input Capture 3 Noise Canceller
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise
Canceler is activated, the input from the Input Capture Pin (ICP3) is filtered. The filter
function requires four successive equal valued samples of the ICP3 pin for changing its
output. The input capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
• Bit 6 – ICES3 - Input Capture 3 Edge Select
This bit selects which edge on the Input Capture Pin (ICP3) that is used to trigger a
capture event. When the ICES3 bit is written to zero, a falling (negative) edge is used
as trigger. When the ICES3 bit is written to one, a rising (positive) edge will trigger the
capture. When a capture is triggered according to the ICES3 setting, the counter value
is copied into the Input Capture Register (ICR3). The event will also set the Input
Capture Flag (ICF3). This can be used to cause an Input Capture Interrupt, if this
interrupt is enabled. When the ICR3 is used as TOP value (see description of the
WGM33:0 bits located in the TCCR3A and the TCCR3B Register), the ICP3 is
disconnected and consequently the input capture function is disabled.
• Bit 5 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 4:3 – WGM31:30 - Waveform Generation Mode
Combined with the WGM31:0 bits found in the TCCR3A Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more information
on the different modes see section "Modes of Operation".
Table 18-16 WGM3 Register Bits
Bit
NA ($91)
Read/Write
Initial Value
Register Bits
Register Bits
WGM31:30
ICNC3
RW
7
0
ICES3
RW
6
0
Res
R
5
0
Value
Value
0xE
0xF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
WGM33
RW
4
0
WGM32
Description
Fast PWM, TOP = ICRn
Fast PWM, TOP = OCRnA
Description
Normal mode of operation
PWM, phase correct, 8-bit
PWM, phase correct, 9-bit
PWM, phase correct, 10-bit
CTC, TOP = OCRnA
Fast PWM, 8-bit
Fast PWM, 9-bit
RW
3
0
CS32
RW
2
0
CS31
RW
1
0
8266A-MCU Wireless-12/09
CS30
RW
0
0
TCCR3B