ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 260

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The procedure for updating ICRn differs from updating OCRnA when used for defining
the TOP value. The ICRn Register is not double buffered. This means that if ICRn is
changed to a low value while the counter is running with no or a low prescaler value,
there is a risk that the newly written ICRn value is lower than the current value of
TCNTn. In consequence the counter will miss the compare match at the TOP value.
The counter must then count to the MAX value (0xFFFF) and wrap around starting at
0x0000 before the compare match can occur. The OCRnA Register is double buffered
though. This feature allows writing the OCRnA I/O location at anytime. When the
OCRnA I/O location is written the new value will be put first into the OCRnA Buffer
Register. The OCRnA Compare Register will then be updated with the value in the
Buffer Register at the next clock cycle of the timer when TCNTn matches TOP. The
update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn
Flag is set.
The definition of TOP with the ICRn Register works well for fixed TOP values.
Combined with ICRn, the OCRnA Register is free to be used for generating a PWM
output on OCnA. However, if the base PWM frequency is actively changed (by
modifying the TOP value), working with the OCRnA as TOP is clearly a better choice
due to its double buffer feature.
In fast PWM mode the compare units allow the generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COMnx1:0 to 3 (see
Table 18-3
on page
256). The actual OCnx value will only be visible on the port pin if the data
direction of the port pin is set to output (DDR_OCnx). The PWM waveform is generated
by setting (or clearing) the OCnx Register at the compare match between OCRnx and
TCNTn, and by clearing (or setting) the OCnx Register at the timer clock cycle the
counter is cleared (changes from TOP to BOTTOM).
The PWM frequency of the output f
can be calculated with the following
OCnxPWM
equation:
f
clk
_
I
/
O
f
=
OCnxPWM
N
⋅
1 (
+
TOP
)
The N variable represents the prescaler divider (1, 8, 64, 256 or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM
(0x0000), the output will be a narrow spike for each TOP+1 timer clock cycle. Setting
the OCRnx equal to TOP will result in a constant high or low output (depending on the
polarity of the output set by the COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1).
This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The
waveform generated will have a maximum frequency of f
= f
/2 when OCRnA is
OCnA
clk_I/O
set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except
the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
18.9.4 Phase Correct PWM Mode
The phase correct Pulse Width Modulation (PWM) mode (WGMn3:0 = 1, 2, 3, 10 or 11)
provides a high resolution phase correct PWM waveform generation option. The phase
correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP
and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while
ATmega128RFA1
260
8266A-MCU Wireless-12/09