ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 112

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.16 TRX_CTRL_2 – Transceiver Control Register 2
9.12.17 ANT_DIV – Antenna Diversity Control Register
112
ATmega128RFA1
Table 9-45 SFD_VALUE Register Bits
This register controls the data rate setting of the radio transceiver.
• Bit 7 – RX_SAFE_MODE - RX Safe Mode
If this bit is set, the next received frame will be protected and not overwritten by
following frames. Set this bit to 0 to release the buffer (and set it again for further
protection).
• Bit 6:2 – Res4:0 - Reserved
• Bit 1:0 – OQPSK_DATA_RATE1:0 - Data Rate Selection
A write access to these register bits sets the OQPSK PSDU data rate used by the radio
transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according
to IEEE 802.15.4. All other values are used in High Data Rate Modes.
Table 9-46 OQPSK_DATA_RATE Register Bits
This register controls the Antenna Diversity.
• Bit 7 – ANT_SEL - Antenna Diversity Antenna Status
Bit
NA ($14C)
Read/Write
Initial Value
Bit
NA ($14C)
Read/Write
Initial Value
Bit
NA ($14D)
Read/Write
Initial Value
Bit
NA ($14D)
Read/Write
Initial Value
Register Bits
SFD_VALUE7:0
Register Bits
OQPSK_DATA_RATE1:0
RX_SAFE_MODE
ANT_DIV_EN
Res1
ANT_SEL
R
3
0
RW
RW
R
7
0
3
0
7
0
Res0
ANT_EXT_SW_EN
R
2
0
Res2
Res4
RW
R
6
0
R
6
0
2
0
Value
Value
OQPSK_DATA_RATE1 OQPSK_DATA_RATE0
0xA7
0
1
2
3
RW
1
0
ANT_CTRL1
Res1
Description
IEEE 802.15.4 compliant value of the SFD
Description
250 kb/s (IEEE 802.15.4 compliant)
500 kb/s
1000 kb/s
2000 kb/s
Res3
R
5
0
RW
R
5
0
1
1
ANT_CTRL0
Res0
Res2
RW
R
4
0
RW
R
0
0
4
0
0
1
8266A-MCU Wireless-12/09
TRX_CTRL_2
TRX_CTRL_2
ANT_DIV
ANT_DIV