ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 359

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8266A-MCU Wireless-12/09
compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A
will be set.
Table 23-5 UPM0 Register Bits
• Bit 3 – USBS0 - Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 23-6 USBS0 Register Bits
• Bit 2:1 – UCSZ01:00 - Character Size
The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of data
bits (Character Size) in the frame that the Receiver and Transmitter use.
Table 23-7 UCSZ0 Register Bits
• Bit 0 – UCPOL0 - Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOL0 bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK0).
Table 23-8 UCPOL0 Register Bits
Register Bits
UPM01:00
Register Bits
USBS0
Register Bits
UCSZ01:00
Register Bits
UCPOL0
Value
Value
Value
Value
0x00
0x01
0x02
0x03
0x00
0x01
0
1
2
3
4
5
6
7
0
1
Description
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Description
1-bit
2-bit
Description
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
Description
Rising XCKn Edge (Transmitted Data
Changed), Falling XCKn Edge (Received
Data Sampled)
Falling XCKn Edge (Transmitted Data
Changed), Rising XCKn Edge (Received
Data Sampled)
ATmega128RFA1
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