ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 96

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
9.8.8.5 AES Interrupt Handling
9.9 Continuous Transmission Test Mode
9.9.1 Overview
9.9.2 Configuration
96
ATmega128RFA1
The status of the security processing is indicated by register AES_STATUS. After a
AES processing time of 24 µs the register bit AES_DONE changes to 1 (register
AES_STATUS) indicating that the security operation has finished (see
Timing Characteristics" on page
The end of the AES processing can also be indicated by the AES_READY Interrupt.
The bit AES_ER of register AES_STATUS is set if the operation has finished with an
error. Otherwise this bit is zero but AES_DONE is ‘1’.
The AES Interrupt handling is slightly different from all other IRQ’s. If the AES_IM Bit
(AES_CTRL Register) and the global interrupt enable flag is set, the AES core can
generate an AES Ready Interrupt (AES_READY). If the IRQ is issued, the
AES_STATUS register must be read to check the finish status of the last operation. If
AES_DONE is set, the last AES operation finished successfully. If AES_ER is set, an
error occurred during the last operation. The AES_ER flag is cleared automatically
during the read access to the AES_STATUS register. The AES_DONE flag is cleared
during the next read or write access to the AES_STATE (AES data) register.
The two status flags must be cleared before a new Interrupt can be issued.
If AES_IM is not set, the processing status can be polled by software (AES_STATUS
register), but no Interrupt occurs.
The 2.4GHz transceiver offers a Continuous Transmission Test Mode to support final
application / production tests as well as certification tests. In this test mode the radio
transceiver transmits continuously a previously transferred frame (PRBS mode) or a
continuous wave signal (CW mode).
In CW mode two different signal frequencies per channel can be transmitted:
• f
• f
Here f
Note that in CW mode it is not possible to transmit a RF signal directly on the channel
center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR
(see section
recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data
for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts
with the PSDU data and is repeated continuously.
All register configurations shall be setup as follows before enabling Continuous
Transmission Test Mode:
• TX channel setting (optional);
• TX output power setting (optional);
• Mode selection (PRBS / CW);
An access to the registers TST_CTRL_DIGI and PART_NUM enables the Continuous
Transmission Test Mode.
1
2
= f
= f
CH
CH
CH
is the channel center frequency programmed by register PHY_CC_CCA.
+ 0.5 MHz
- 0.5 MHz
"Introduction – IEEE 802.15.4-2006 Frame Format" on page
507).
8266A-MCU Wireless-12/09
"Digital Interface
61). It is

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