ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 129

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.46 CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2
8266A-MCU Wireless-12/09
This register is a control register for RX_AACK and contains a part of the CSMA_SEED
for the CSMA-CA algorithm.
• Bit 7:6 – AACK_FVN_MODE1:0 - Acknowledgment Frame Filter Mode
The frame control field of the MAC header (MHR) contains a frame version subfield.
The setting of AACK_FVN_MODE specifies the frame filtering behavior of the radio
transceiver. According to the content of these register bits the radio transceiver passes
frames with a specific frame version number, number group or independent of the
frame version number. Thus the register bits AACK_FVN_MODE define the maximum
acceptable frame version. Received frames with a higher frame version number than
configured do not pass the address filter and are not acknowledged.
Table 9-69 AACK_FVN_MODE Register Bits
• Bit 5 – AACK_SET_PD - Set Frame Pending Sub-field
The content of AACK_SET_PD bit is copied into the frame pending subfield of the
acknowledgment frame if the acknowledgment is the answer to a data request MAC
command frame. If in addition the bits AACK_FVN_MODE of this register are
configured to accept frames with a frame version other than 0 or 1, the content of
register bit AACK_SET_PD is also copied into the frame pending subfield of the
acknowledgment frame for any MAC command frame with a frame version of 2 or 3 that
have the security enabled subfield set to 1. This is done in the assumption that a future
version of the IEEE 802.15.4 standard might change the length or structure of the
auxiliary security header, so that it is not possible to safely detect whether the MAC
command frame is actually a data request command or not.
Bit
NA ($16E)
Read/Write
Initial Value
Bit
NA ($16E)
Read/Write
Initial Value
Bit
NA ($16E)
Read/Write
Initial Value
Bit
NA ($16E)
Read/Write
Initial Value
Register Bits
AACK_FVN_MODE1:0
AACK_I_AM_COORD
AACK_FVN_MODE1
CSMA_SEED_11
AACK_SET_PD
RW
RW
RW
RW
7
0
5
0
3
0
1
1
Value
0
1
2
3
Description
Acknowledge frames with version number 0
Acknowledge frames with version number 0
or 1
Acknowledge frames with version number 0
or 1 or 2
Acknowledge frames independent of frame
version number
AACK_FVN_MODE0
CSMA_SEED_12
CSMA_SEED_10
AACK_DIS_ACK
ATmega128RFA1
RW
RW
RW
RW
6
1
4
0
2
0
0
0
CSMA_SEED_1
CSMA_SEED_1
CSMA_SEED_1
CSMA_SEED_1
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