ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 418

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6.2 ADC Input Channels
418
ATmega128RFA1
the MUX4:0 bits need to be modified then a write access to the MUX4:0 bits is
sufficient.
The ADC input channels can be changed while the ADC is running under the condition
that the previous channel was a single-ended one. Changing between differential
channels however requires that the ADC is disabled and enabled again to make the
ADC go through the initial start-up phase.
If changing from single-ended to single-ended or from single-ended to differential input
channels a settling phase is automatically inserted by the ADC interface logic after the
input channel is modified. The settling phase is required by the ADC and the gain
amplifier to stabilize. If a conversions start is requested during this settling phase, by
setting ADSC or by a trigger event in Auto Triggered mode then the conversion is
started only after the settling phase has completed.
In case the MUXn bits are altered during an ongoing conversion, the ADC input channel
is changed after the conversion has completed. MUXn changes occurring during the
tracking phase, which follows a conversion, will stop the tracking phase and the ADC
settling phase will be entered.
In Free Running mode MUXn can also be modified. In this case the ADC input channel
is changed after the conversion end or from the subsequent tracking phase. As a
consequence the time from one conversion to the next is extended by the duration of
the ADC settling phase.
The ADC settling time t
configuration of the ADSUT4:0 and ADTHT1:0 bits as shown in
Additionally a synchronization delay t
required between changing the ADC input channel selection and the beginning of the
settling phase. For details see the timing diagrams
27-10 on
If the analog input signal encounters large variations it can be useful to manually reset
the ADC and the gain amplifier before starting a new conversion. To achieve this, the
settling phase can be forced without modifying MUXn by writing a logic one to the
Analog Channel Change bit ACCH in ADCSRB. Using the ACCH bit is only
recommended for single-ended input channels. For differential input channels the ADC
and the gain amplifier can be reset if the ADC is disabled and enabled again.
Table 27-6. Settling Time after Channel Changes
Channel Transition
Single-Ended or Differential to Single-Ended
Single-Ended to Differential
Differential to Differential
page 419.
ASET
depends on the previous and the new channel and on the
CHDLY
Settling Time t
ADTHT+2
4(ADSUT+1) + 2(ADTHT+2)
Requires the ADC to be disabled and enabled
again.
from 2 CPU to 2 ADC Clock cycles is
Figure 27-9 on
ASET
in ADC Clock Cycles
page 419 and
8266A-MCU Wireless-12/09
Table 27-6
below.
Figure