ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 266

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
18.11 Register Description
18.11.1 TCCR1A – Timer/Counter1 Control Register A
266
ATmega128RFA1
Figure 18-13 shows the same timing data, but with the prescaler enabled.
Figure 18-13. Timer/Counter Timing Diagram with Prescaler (f
• Bit 7:6 – COM1A1:0 - Compare Output Mode for Channel A
The COM1A1:0 bits control the output compare behavior of pin OC1A. If one or both of
the COM1A1:0 bits are written to one, the OC1A output overrides the normal port
functionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC1A pin must be set in order to enable the
output driver. When the OC1A is connected to the pin, the function of the COM1A1:0
bits is dependent of the WGM13:0 bits setting. The following table shows the
COM1A1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-6 COM1A Register Bits
• Bit 5:4 – COM1B1:0 - Compare Output Mode for Channel B
Bit
NA ($80)
Read/Write
Initial Value
Register Bits
COM1A1:0
and ICF n
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
TCNTn
TCNTn
as TOP)
OCRnx
(clk
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10
RW
7
0
RW
6
0
TOP - 1
TOP - 1
Old OCRnx Value
RW
5
0
Value
0
1
2
3
RW
4
0
TOP
TOP
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on Compare
Match.
Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).
Set OCnA/OCnB/OCnC on Compare Match
(set output to high level).
RW
3
0
RW
2
0
BOTTOM
TOP - 1
clk_I/O
New OCRnx Value
RW
1
0
/8)
8266A-MCU Wireless-12/09
RW
BOTTOM + 1
0
0
TOP - 2
TCCR1A

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