ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 157

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.1 Idle Mode
12.2.2 ADC Noise Reduction Mode
8266A-MCU Wireless-12/09
Power-down
Power-save
Standby
Extended
Standby
(1)
Active Clock Domains
To enter any of the sleep modes, the SE bit in in the SMCR register (see
Sleep Mode Control Register" on page
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register
select which sleep mode will be activated by the SLEEP instruction. See chapter
"Register Description" on page 166
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up.
The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. Note that SRAM data retention must be enabled in some sleep modes to
preserve the memory contents (see section
If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
When the SM2:0 bits are written to 000 in the SMCR register, the SLEEP instruction
makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART,
Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and
Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC
is enabled, a conversion starts automatically when this mode is entered.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode (ADCNRM), stopping the CPU but allowing the ADC, the
external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the
Watchdog to continue operating (if enabled). This sleep mode basically halts clk
clk
This improves the noise environment for the ADC, enabling higher resolution
measurements. If the ADC is enabled, a conversion starts automatically when this
mode is entered. Apart form the ADC Conversion Complete interrupt, only an External
Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire
serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt,
Notes:
FLASH
CPU
, and clk
, while allowing the other clocks to run.
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
X
X
(2)
FLASH
Oscillators
X
X
, while allowing the other clocks to run.
X
X
(2)
(2)
X
X
X
X
(3)
(3)
(3)
(3)
for a summary.
X
X
X
X
166) must be written to logic one and a SLEEP
"SRAM with Data Retention" on page
X
X
Wake-up Sources
ATmega128RFA1
X
X
X
X
"SMCR –
X
X
X
X
CPU
163).
and
157
I/O
X
X
X
X
,