ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 317

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.1 Force Output Compare
21.6.2 Compare Match Blocking by TCNT2 Write
21.6.3 Using the Output Compare Unit
21.7 Compare Match Output Unit
8266A-MCU Wireless-12/09
The OCR2x Register access may seem complex, but this is not the case. When the
double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if
double buffering is disabled the CPU will access the OCR2x directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare
match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be
updated as if a real compare match had occurred (the COM2x1:0 bits settings define
whether the OC2x pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any compare match that
occurs in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt
when the Timer/Counter clock is enabled.
Since writing TCNT2 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT2 when using the
Output Compare channel, independently of whether the Timer/Counter is running or
not. If the value written to TCNT2 equals the OCR2x value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2
value equal to BOTTOM when the counter is down-counting.
The setup of the OC2x should be performed before setting the Data Direction Register
for the port pin to output. The easiest way of setting the OC2x value is to use the Force
Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its
value even when changing between Waveform Generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare
value. A change of the COM2x1:0 bits will take effect immediately.
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform
Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the
next compare match. Also, the COM2x1:0 bits control the OC2x pin output source.
Figure 20-7 shows a simplified schematic of the logic affected by the COM2x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only
the parts of the general I/O Port Control Registers (DDR and PORT) that are affected
by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for
the internal OC2x Register, not the OC2x pin.
The general I/O port function is overridden by the Output Compare (OC2x) from the
Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as
output before the OC2x value is visible on the pin. The port override function is
independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state
before the output is enabled. Note that some COM2x1:0 bit settings are reserved for
certain modes of operation. See section
"Register Description" on page 323
ATmega128RFA1
for details.
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