ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 75

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6.1.2 Frame Receive Procedure
9.6.1.3 Configuration
8266A-MCU Wireless-12/09
converter (RX ADC) and generates a digital RSSI signal. The ADC output signal is
sampled and processed further by the digital base band receiver (RX BBP).
The RX BBP performs additional signal filtering and signal synchronization. The
frequency offset of each frame is calculated by the synchronization unit and is used
during the remaining receive process to correct the offset. The receiver is designed to
handle frequency and symbol rate deviations up to ±120 ppm caused by combined
receiver and transmitter deviations. For details refer to chapter
Specifications" on page
in the Frame Buffer.
In Basic Operating Mode (see
frame is indicated by a TRX24_RX_START interrupt. Accordingly its end is signalized
by a TRX24_RX_END interrupt. Based on the quality of the received signal a link
quality indicator (LQI) is calculated and appended to the frame. For details refer to.
Additional signal processing is applied to the frame data to provide further status
information like ED value (register PHY_ED_LEVEL) and FCS correctness (register
PHY_RSSI).
Beyond these features the Extended Operating Mode of the radio transceiver supports
address filtering and pending data indication. For details refer to
Mode" on page 43.
The frame receive procedure including the radio s setup for reception and reading
PSDU data from the Frame Buffer is described in
84.
In Basic Operating Mode the receiver is enabled by writing command RX_ON to the
TRX_CMD bits of register TRX_STATE in the states TRX_OFF or PLL_ON. Similarly in
Extended Operating Mode the receiver is enabled for RX_AACK operation from the
states TRX_OFF or PLL_ON by writing the command RX_AACK_ON. There is no
additional configuration required to receive IEEE 802.15.4 compliant frames when using
the Basic Operating Mode. However, the frame reception in the Extended Operating
Mode requires further register configurations. For details refer to
Mode" on page
The receiver has an outstanding sensitivity performance of -100 dBm. At certain
environmental conditions or for High Data Rate Modes (see
page 86)
adjusting
RX_PDT_LEVEL bits of register RX_SYN. Received signals with a RSSI value below
the threshold do not activate the demodulation process.
Furthermore, it may be useful to protect a received frame against overwriting by
subsequent received frames.
A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE
(TRX_CTRL_2) set (refer to
frame has been received, the buffer is protected for new incoming frames and the
receiver remains in RX_ON or RX_AACK_ON state until the RX_SAFE_MODE bit is
cleared by the controller. The Frame Buffer content is only protected if the FCS is valid.
A Static Frame Buffer Protection is enabled with bit RX_PDT_DIS of register RX_SYN
set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is
detected until the register bit RX_PDT_DIS is set back.
it may be useful to manually decrease this sensitivity. This is achieved by
the
43.
detector
507. Finally the signal is demodulated and the data are stored
threshold
"Dynamic Frame Buffer Protection" on page
"Basic Operating Mode" on page
of
the
synchronization
"Frame Receive Procedure" on page
ATmega128RFA1
"High Data Rate Modes" on
35), the reception of a
"Extended Operating
"Extended Operating
header
"General RF
91). After a
using
the
75