ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 477

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.8 Serial Downloading
31.8.1 Serial Programming Pin Mapping
8266A-MCU Wireless-12/09
Table 31-14. Parallel Programming Characteristics, V
Both the Flash and EEPROM memory arrays can be programmed using a serial
programming bus while RSTN is pulled to DVSS. The serial programming interface
consists of pins SCK, PDI (input) and PDO (output). After RSTN is set low, the
Programming Enable instruction needs to be executed first before program/erase
operations can be executed. NOTE, in
programming is listed.
Table 31-15. Pin Mapping Serial Programming
Notes:
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TSTRNH
DVXH
XLXH
XHXL
XLDX
XLWL
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
XLOL
BVDV
OLDV
OHDZ
Symbol
PDO
SCK
1. t
2. t
PDI
bits commands.
WLRH
WLRH_CE
Parameter
Delay TST High before RSTN High
Data and Control Valid before CLKI High
CLKI Low to CLKI High
CLKI Pulse Width High
Data and Control Hold after CLKI Low
CLKI Low to WR
CLKI Low to PAGEL high
PAGEL low to CLKI high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR
PAGEL Low to WR
BS2/1 Valid to WR
___
WR
___
WR
___
WR
___
WR
CLKI Low to OE
BS1 Valid to DATA valid
OE
OE
__
__
Low to DATA Valid
High to DATA Tri-stated
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock
Pulse Width Low
Low to RDY/BSY
Low to RDY/BSY
Low to RDY/BSY
is valid for the Chip Erase command.
___
__
___
___
Low
Low
___
___
___
___
Low
Pins
Low
PB2
PB3
PB1
Low
Low
High
High for Chip Erase
(1)
Table 31-15
(2)
ATmega128RFA1
I/O
DEVDD
below, the pin mapping for serial
O
I
I
Min
200
150
150
150
150
3.7
67
67
67
67
67
67
67
12
0
0
0
0
0
0
= 3.3V ± 10%
Typ
Serial Data Out
Serial Data In
Description
Serial Clock
Max
14.5
250
250
250
4.5
1
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
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