ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 267

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8266A-MCU Wireless-12/09
The COM1B1:0 bits control the output compare behavior of pin OC1B. If one or both of
the COM1B1:0 bits are written to one, the OC1B output overrides the normal port
functionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC1B pin must be set in order to enable the
output driver. When the OC1A is connected to the pin, the function of the COM1B1:0
bits is dependent of the WGM13:0 bits setting. The following table shows the
COM1B1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-7 COM1B Register Bits
• Bit 3:2 – COM1C1:0 - Compare Output Mode for Channel C
The COM1C1:0 bits control the output compare behavior of pin OC1C. If one or both of
the COM1C1:0 bits are written to one, the OC1C output overrides the normal port
functionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC1C pin must be set in order to enable the
output driver. When the OC1A is connected to the pin, the function of the COM1C1:0
bits is dependent of the WGM13:0 bits setting. The following table shows the
COM1C1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-8 COM1C Register Bits
• Bit 1:0 – WGM11:10 - Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more information
on the different modes see section "Modes of Operation".
Table 18-9 WGM1 Register Bits
Register Bits
COM1B1:0
Register Bits
COM1C1:0
Register Bits
WGM11:10
Value
Value
Value
0x0
0x1
0
1
2
3
0
1
2
3
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on Compare
Match.
Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).
Set OCnA/OCnB/OCnC on Compare Match
(set output to high level).
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on Compare
Match.
Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).
Set OCnA/OCnB/OCnC on Compare Match
(set output to high level).
Description
Normal mode of operation
PWM, phase correct, 8-bit
ATmega128RFA1
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