ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 67

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5.2.3 Automatic FCS generation
9.5.2.4 Automatic FCS check
9.5.3 Received Signal Strength Indicator (RSSI)
9.5.3.1 Overview
8266A-MCU Wireless-12/09
Example:
Consider a 5 octet ACK frame. The MHR field consists of
The leftmost bit (b
The leftmost bit (r
The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1
(reset value). This allows the radio transceiver to autonomously compute the FCS. For
a frame with a frame length specified as N (3
first N-2 octets in the Frame Buffer and the resulting FCS field is transmitted in place of
the last two octets from the Frame Buffer.
If the automatic FCS generation of the radio transceivers is enabled, the Frame Buffer
write access can be stopped right after MAC payload. There is no need to write FCS
dummy bytes.
In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the
ACK frame is always automatically generated by the radio transceiver, independent of
the TX_AUTO_CRC_ON setting.
Example:
A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a
Frame Buffer write access of five bytes (the last two bytes can be omitted). The first
three bytes are used for FCS generation; the last two bytes are replaced by the
internally calculated FCS.
An automatic FCS check is applied on each received frame with a frame length N
The bit RX_CRC_VALID of register PHY_RSSI is set if the FCS of a received frame is
valid. The register bit is updated when issuing a TRX24_RX_END interrupt and remains
valid until a new frame reception causes the next TRX24_RX_END interrupt.
In RX_AACK mode, the radio transceiver rejects the frame and the TRX24_RX_END
interrupt is not issued if the FCS of the received frame is not valid.
In TX_ARET mode, the FCS and the sequence number of an ACK are automatically
checked. The ACK is not accepted if one of those is not correct.
The Received Signal Strength Indicator is characterized by:
• Minimum RSSI level is -90 dBm (RSSI_BASE_VAL);
• Dynamic range is 81 dB;
• Minimum RSSI value is 0;
• Maximum RSSI value is 28.
The RSSI is a 5-bit value indicating the receive power in the selected channel in steps
of 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others. Only the
0100 0000 0000 0000 0101 0110.
0010 0111 1001 1110.
0
0
) is transmitted first in time.
) is transmitted first in time. The FCS is in this case
N
ATmega128RFA1
127), the FCS is calculated on the
2.
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