ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 41

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.1.4.4 Reset Procedure
8266A-MCU Wireless-12/09
t
BUSY_TX state and the internally generated SHR is transmitted. After that the PSDU
data are transmitted from the Frame Buffer.
After completing the frame transmission, indicated by the TRX24_TX_END interrupt,
the PLL settles back to the receive frequency within t
If during TX_BUSY the radio transmitter is programmed to change to a receive state it
automatically proceeds the state change to RX_ON state after finishing the
transmission.
The radio transceiver reset procedure is shown in
Figure 9-17. Reset Procedure
TRXRST = “1” resets all radio transceiver registers to their default values.
The radio transceiver reset is released automatically after 3 AVR clock cycles and the
wake-up sequence without restarting XOSC and DVREG, nevertheless an FTN
calibration cycle is performed, refer to
that the TRX_OFF state is entered.
Figure 9-17 above
transceiver is in any state but not in SLEEP state.
If the radio transceiver was in SLEEP state, the SLPTR bit in the TRXPR register must
be cleared prior to clearing the TRXRST bit in order to enter the TRX_OFF state.
Otherwise the radio transceiver enters the SLEEP state immediately.
If the radio transceiver was in SLEEP state and the Transceiver Clock is not selected as
the microcontroller clock source, the XOSC is enabled before entering TRX_OFF state.
If register TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during
system initialization until the radio transceiver reaches TRX_OFF, do not try to initiate a
further state change while the radio transceiver is in this state.
Note that before accessing the radio transceiver module the TRX24_AWAKE event
should be checked.
TR10
Note:
E v e n t
S ta te
B lo c k
T R X R S T
T im e
= 16 µs after initiating the transmission, the radio transceiver changes into
1. Timing parameter t
2. If TRXRST is set during radio transceiver SLEEP state, the XOSC startup delay is
v a rio u s
Interface Timing Characteristics" on page
extended by the XOSC startup time.
X O S C , D V R E G e n a b le d
0
illustrates the radio transceiver reset procedure if the radio
3 x A V R c lo c k
TR13
x
= 37 s refers to
x + 1 0
> t1 1
"Automatic Filter Tuning (FTN)" on page 83.
t
T R 1 3
F T N
Table 9-3 on
Figure 9-17
507.
TR11
ATmega128RFA1
x + 4 0
[T R X 2 4 _ A W A K E IR Q ]
T R X _ O F F
= 32 s in state PLL_ON.
X O S C , D V R E G e n a b le d
page 42; t
below.
11
refers to
T im e [µ s ]
"Digital
After
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