ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 348

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.6.4 Parity Generator
23.6.5 Disabling the Transmitter
23.7 Data Reception – The USART Receiver
23.7.1 Receiving Frames with 5 to 8 Data Bits
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ATmega128RFA1
The parity generator calculates the parity bit for the serial frame data. When parity bit is
enabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
The disabling of the transmitter (setting the TXEN to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the transmit shift register
and transmit buffer register do not contain data to be transmitted. The transmitter will no
longer override the TxDn pin when disabled.
The USART receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB register to one. When the receiver is enabled, the normal pin operation of the
RxDn pin is overridden by the USART and given the function as the receiver’s serial
input. The baud rate, mode of operation and frame format must be set up once before
any serial reception can be done. If synchronous operation is used, the clock on the
XCKn pin will be used as transfer clock.
The receiver starts data reception when it detects a valid start bit. Each bit that follows
the start bit will be sampled at the baud rate or XCKn clock, and shifted into the receive
shift register until the first stop bit of a frame is received. A second stop bit will be
ignored by the receiver. When the first stop bit is received, i.e., a complete serial frame
is present in the receive shift register, the contents of the shift register will be moved
into the receive buffer. The receive buffer can then be read by reading the UDRn I/O
location.
The following code example shows a simple USART receive function based on polling
of the Receive Complete Flag (RXCn). When using frames with less than eight bits the
most significant bits of the data read from the UDRn will be masked to zero. The
USART has to be initialized before the function can be used. The function simply waits
for data to be present in the receive buffer by checking the RXCn flag before reading
the buffer and returning the value.
Assembly Code Example
USART_Receive:
; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDRn
ret
(1)
8266A-MCU Wireless-12/09