ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 220

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2.2 EICRB – External Interrupt Control Register B
220
ATmega128RFA1
Table 16-128 ISC1 Register Bits
• Bit 1:0 – ISC01:00 - External Interrupt 0 Sense Control Bit
Table 16-129 ISC0 Register Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in the following tables. Edges on
INT7:4 are registered asynchronously. Pulses on INT7:4 pins wider than the minimum
pulse width of typical 50 ns will generate an interrupt. Shorter pulses are not
guaranteed to generate an interrupt. If low level interrupt is selected, the low level must
be held until the completion of the currently executing instruction to generate an
interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long
as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it
is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK
Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be
cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register
before the interrupt is re-enabled. When changing the ISCn1/ISCn0 bits, the interrupt
must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise
an interrupt can occur when the bits are changed.
• Bit 7:6 – ISC71:70 - External Interrupt 7 Sense Control Bit
Table 16-130 ISC7 Register Bits
Bit
NA ($6A)
Read/Write
Initial Value
Register Bits
ISC11:10
Register Bits
ISC01:00
Register Bits
ISC71:70
ISC71
RW
7
0
ISC70
RW
6
0
ISC61
RW
5
0
Value
Value
Value
0x00
0x01
0x02
0x03
0x00
0x01
0x02
0x03
0x00
ISC60
RW
4
0
Description
The low level of INTn generates an interrupt
request.
Any edge of INTn generates asynchronously
an interrupt request.
The falling edge of INTn generates
asynchronously an interrupt request.
The rising edge of INTn generates
asynchronously an interrupt request.
Description
The low level of INTn generates an interrupt
request.
Any edge of INTn generates asynchronously
an interrupt request.
The falling edge of INTn generates
asynchronously an interrupt request.
The rising edge of INTn generates
asynchronously an interrupt request.
Description
The low level of INTn generates an interrupt
ISC51
RW
3
0
ISC50
RW
2
0
ISC41
RW
1
0
8266A-MCU Wireless-12/09
ISC40
RW
0
0
EICRB