ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 413

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.4 Starting a Conversion
27.5 Pre-scaling and Conversion Timing
27.5.1 Prescaler
8266A-MCU Wireless-12/09
A single conversion is started by writing a logical one to the ADC Start Conversion bit,
ADSC. This bit stays high as long as the conversion is in progress and will be cleared
by hardware when the conversion is completed. If a different data channel is selected
while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto
Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA.
The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB
(See description of the ADTS bits for a list of the trigger sources). When a positive edge
occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is
started. This provides a method of starting conversions at fixed intervals. If the trigger
signal still is set when the conversion completes, a new conversion will not be started. If
another positive edge occurs on the trigger signal during conversion, the edge will be
ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or
the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered
without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.
Figure 27-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new
conversion as soon as the ongoing conversion has finished. The ADC then operates in
Free Running mode, constantly sampling and updating the ADC Data Register. The first
conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this
mode the ADC will perform successive conversions independently of whether the ADC
Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in
ADCSRA to one. ADSC can also be used to determine if a conversion is in progress.
The ADSC bit will be read as one during a conversion, independently of how the
conversion was started.
By default, the successive approximation circuitry requires an input clock frequency
between 50 kHz and 4 MHz. If a lower resolution than 10 bits is needed, the input clock
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADTS[2:0]
DETECTOR
EDGE
ADATE
ATmega128RFA1
START
CONVERSION
PRESCALER
LOGIC
CLK
ADC
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