ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 414

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.5.2 Start-Up Timing
414
ATmega128RFA1
frequency to the ADC can be as high as 8 MHz to get a higher sample rate. For
differential input channels the ADC clock speed is restricted to a maximum of 2 MHz.
Figure 27-3. ADC Prescaler
The ADC module contains a prescaler, which generates an acceptable ADC clock
frequency from any CPU frequency above 100 kHz. The pre-scaling is set by the ADPS
bits in ADCSRA. The prescaler starts counting from the moment when the ADC is
enabled. The prescaler keeps running for as long as the ADEN bit is set, and is
continuously reset when ADEN is low.
The ADC is enabled by setting the ADEN bit in ADCSRA. First the analog voltage
regulator is powered up which takes t
Characteristics" on page
ADCSRB.
After AVDD has stabilized, the ADC is started. The ADC start-up time has a length of
t
differential input channels are used, then an additional initialization period t
required by the gain amplifier. This period is configured by the Track-And-Hold Time
bits, ADTHT1:0 in ADCSRC. ADSUT4:0 and ADTHT1:0 are fixed numbers of ADC
clock cycles and can be setup for different ADC clock speeds.
The minimum required ADC start-up time is 20 µs. Note that for the maximum ADC
speed of 8 MHz the start-up time can not be set higher than 16 µs in ADSUT4:0. Under
this condition the user has either to ensure that a conversion is not started earlier than
20 µs after the ADC is enabled or the first conversion result should be discarded.
For a summary of start-up times and sequences see
below,
Table 27-1. Start-Up Time, Single Ended Channels
Table 27-2. Start-Up Time, Differential Channels
ADSU
Parameter
ADC Start-Up Time t
Parameter
ADC Start-Up Time t
and can be adjusted by the Start-Up time bits ADSUT4:0 in ADCSRC. If
Figure 27-4 on
ADEN
START
ADSU
ADSU
page 415 and
ADPS0
ADPS1
ADPS2
CK
503). A stable AVDD is indicated by the AVDDOK bit in
Figure 27-5 on
Reset
AVREG
7-BIT ADC PRESCALER
Duration in ADC Clock Cycles
4(ADSUT+1), minimum 20 µs
Duration in ADC Clock Cycles
4(ADSUT+1), minimum 20 µs
ADC CLOCK SOURCE
(see
page 415.
"Power Management Electrical
Table 27-1
8266A-MCU Wireless-12/09
below,
Table 27-2
AINIT
is