ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 185
![IC AVR MCU 2.4GHZ XCEIVER 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 185 of 385
- Download datasheet (8Mb)
Asynchronous
Operational Range
2467V–AVR–02/11
Figure 85. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(C) marks a stop bit of full length. The early start bit detection influences the operational range of
the receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see
Table
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
baud rate. R
the receiver baud rate.
Table 75
normal speed mode has higher toleration of baud rate variations.
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver
Sum of character size and parity size (D = 5 to 10-bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
RxD
75) base frequency, the Receiver will not be able to synchronize the frames to the start bit.
M
and
= 5 for Double Speed mode.
R
slow
fast
Table 76
is the ratio of the fastest incoming data rate that can be accepted in relation to
=
Figure
------------------------------------------ -
S 1
–
1
1
list the maximum receiver baud rate error that can be tolerated. Note that
(
D
+
2
85. For Double Speed mode the first low level must be delayed to (B).
+
D S ⋅
1
3
2
)S
+
4
S
F
5
3
6
7
4
8
STOP 1
9
5
F
10
= 8 for Normal Speed and S
M
R
= 9 for Normal Speed and
fast
(A)
0/1
6
=
0/1
-----------------------------------
(
D
(B)
0/1
0/1
(
+
D
1
+
)S
2
ATmega128
)S
+
S
M
(C)
F
= 4
185
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