ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 18

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Price
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SRAM Data
Memory
18
ATmega128
The Atmel
as listed in
Table 1. Memory Configurations
Figure 9
The ATmega128 is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended
I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be
used. The Extended I/O space does not exist when the ATmega128 is in the ATmega103 com-
patibility mode.
In normal mode, the first 4352 Data Memory locations address both the Register file, the I/O
Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the
Register file, the next 64 location the standard I/O memory, then 160 locations of Extended I/O
memory, and the next 4096 locations address the internal data SRAM.
In ATmega103 compatibility mode, the first 4096 Data Memory locations address both the Reg-
ister file, the I/O Memory and the internal data SRAM. The first 32 locations address the Register
file, the next 64 location the standard I/O memory, and the next 4000 locations address the inter-
nal data SRAM.
An optional external data SRAM can be used with the ATmega128. This SRAM will occupy an
area in the remaining address locations in the 64K address space. This area starts at the
address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM
occupies the lowest 4352bytes in normal mode, and the lowest 4096bytes in the ATmega103
compatibility mode (Extended I/O not present), so when using 64Kbyte (65536 bytes) of Exter-
nal Memory, 61184bytes of External Memory are available in normal mode, and 61440 bytes in
ATmega103 compatibility mode. See
to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data memory
locations, the external data SRAM is accessed using the same instructions as for the internal
data memory access. When the internal data memories are accessed, the read and write strobe
pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is
enabled by setting the SRE bit in the MCUCR Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the
internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP
take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine
calls and returns take three clock cycles extra because the two-byte program counter is pushed
and popped, and external memory access does not take advantage of the internal pipe-line
memory access. When external SRAM interface is used with wait-state, one-byte external
access takes two, three, or four additional clock cycles for one, two, and three wait-states
respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles
more than specified in the instruction set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
Configuration
Normal mode
ATmega103 Compatibility
mode
shows how the ATmega128 SRAM Memory is organized.
®
Table
AVR
®
1.
ATmega128 supports two different configurations for the SRAM data memory
Internal SRAM Data Memory
“External Memory Interface” on page 25
4000
4096
External SRAM Data Memory
up to 64K
up to 64K
for details on how
2467V–AVR–02/11

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