ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 32

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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External Memory
Control Register B –
XMCRB
Using all Locations of
External Memory
Smaller than 64 Kbyte
32
ATmega128
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise
be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so
even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is
one.
• Bit 6..4 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte.
If the full 60 Kbyte address space is not required to access the External Memory, some, or all,
Port C pins can be released for normal Port Pin function as described in
“Using all 64 Kbyte Locations of External Memory” on page
bits to access all 64 Kbyte locations of the External Memory.
Table 5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled
Since the external memory is mapped after the internal memory as shown in
external memory is not addressed when addressing the first 4,352 bytes of data space. It may
appear that the first 4,352 bytes of the external memory are inaccessible (external memory
addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64
Kbyte, for example 32 Kbyte, these locations are easily accessed simply by addressing from
address 0x8000 to 0x90FF. Since the External Memory Address bit A15 is not connected to the
external memory, addresses 0x8000 to 0x90FF will appear as addresses 0x0000 to 0x10FF for
the external memory. Addressing above address 0x90FF is not recommended, since this will
address an external memory location that is already accessed by another (lower) address. To
the Application software, the external 32 Kbyte memory will appear as one linear 32 Kbyte
address space from 0x1100 to 0x90FF. This is illustrated in
refers to the ATmega103 compatibility mode, configuration A to the non-compatible mode.
When the device is set in ATmega103 compatibility mode, the internal address space is 4,096
bytes. This implies that the first 4,096 bytes of the external memory can be accessed at
Bit
Read/Write
Initial Value
XMM2
0
0
0
0
1
1
1
1
XMM1
0
0
1
1
0
0
1
1
XMBK
R/W
7
0
XMM0
0
1
0
1
0
1
0
1
R
6
0
# Bits for External Memory Address
8 (Full 60 Kbyte space)
7
6
5
4
3
2
No Address high bits
R
5
0
R
4
0
R
3
0
XMM2
R/W
2
0
Figure
34, it is possible to use the XMMn
XMM1
R/W
1
0
Released Port Pins
None
PC7
PC7 - PC6
PC7 - PC5
PC7 - PC4
PC7 - PC3
PC7 - PC2
Full Port C
17. Memory configuration B
Table
XMM0
R/W
0
0
5. As described in
XMCRB
Figure
2467V–AVR–02/11
11, the

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