SLRC40001T/OFE,112 NXP Semiconductors, SLRC40001T/OFE,112 Datasheet - Page 109
SLRC40001T/OFE,112
Manufacturer Part Number
SLRC40001T/OFE,112
Description
IC I.CODE SLRC400 READER 32-SOIC
Manufacturer
NXP Semiconductors
Series
I-Coder
Datasheets
1.SLRC40001TOFE112.pdf
(130 pages)
2.SLRC40001TOFE112.pdf
(132 pages)
3.SLRC40001TOFE112.pdf
(101 pages)
Specifications of SLRC40001T/OFE,112
Rf Type
Read Only
Frequency
13.56MHz
Features
ISO15693, ISO18000-3
Package / Case
32-SOIC (0.300", 7.50mm Width)
Product
RFID Readers
Operating Temperature Range
- 25 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1124-5
935269551112
SLRC400
SLRC41TOFED
935269551112
SLRC400
SLRC41TOFED
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Philips Semiconductors
I•CODE Reader IC
16.6.2.2 CRC-Coprocessor Settings
For the CRC-Coprocessor the following parameters may be configured:
The CRC polynomial for the 8-bit CRC is fixed to
The CRC polynomial for the 16-bit CRC is fixed to
16.6.2.3 Status Flags of the CRC-Coprocessor
The status flag CRCReady indicates, that the CRC-Coprocessor has finished processing of all data bytes
found in the FIFO buffer. With the CRCReady flag setting to 1, an interrupt is requested with TxIRq being set.
This supports interrupt driven usage of the CRC-Coprocessor.
When CRCReady and TxIRq are set to 1, respectively, the content of the CRCResultLSB- and
CRCResultMSB-register and the flag CRCErr is valid.
The CRCResultLSB- and CRCResultMSB-register hold the content of the CRC register, the CRCErr flag
indicates CRC validity for the processed data.
16.7 Error Handling during Command Execution
If any error is detected during command execution, this is shown by setting the status flag Err in the
PrimaryStatus Register. For information about the cause of the error, the µ-Processor may evaluate the
status flags in the ErrorFlag Register.
Bit-Processing Direction
CRC Register Length
CRC Preset Value
CRC Algorithm
Parameter
Error Flag of the ErrorFlag Register
AccessError
FramingErr
FIFOOvl
CRCErr
CollErr
1 = Algorithm according ISO 15693 or according
Shift the MSBit or LSBit first into the CRC-
Table 16-5: CRC-Coprocessor Parameters
0 = algorithm according to I•CODE1
Table 16-6: Error Flags Overview
8 Bit or 16 Bit CRC
ISO/IEC3309
register
Value
Any
x
8
x
16
+
109
+
x
4
x
+
12
x
+
3
x
+
5
x
+
Product Specification Rev. 3.1 August 2004
2
1
+
.
WriteE2, ReadE2, LoadConfig
Not related to a command
Receive, Transceive, CalcCRC
Receive, Transceive
Receive, Transceive
1
.
Related to Command
CRCPresetLSB,
CRCPresetMSB
CRCMSBFirst
CRC3309
CRC8
Bit
ChannelRedundancy
ChannelRedundancy
ChannelRedundancy
SL RC400
CRCPresetLSB,
CRCPresetMSB
Register
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