LP3907QTLX-VXSS/NOPB National Semiconductor, LP3907QTLX-VXSS/NOPB Datasheet - Page 11

• Manufacturer Part Number: LP3907QTLX-VXSS/NOPB
• Description: IC REG BUCK SYNC-2 LDO-2 25MSMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3907QTLX-VXSS/NOPB

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 2.1MHz
• Voltage/current - Output 1: 1.8V, 1A
• Voltage/current - Output 2: 3.3V, 600mA
• Voltage/current - Output 3: 2.8V, 300mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 2.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 25-UFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

V
V
nPOR
nPOR
threshold
VOL
IL
IH
I/O Electrical Characteristics
Unless otherwise noted: Typical values and limits appearing in normal type apply for T
type apply over the entire junction temperature range for operation, T
Power On Reset Threshold/Function (POR)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
= 140°C (typ.)
Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MILSTD - 883 3015.7)
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
dissipation of the device in the application (P
following equation: T
Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: C
Note 9: The device maintains a stable, regulated output voltage without a load.
Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal value.
Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at V
Note 12: V
Note 13: This specification is guaranteed by design.
Note 14: The I
bus, or it can be defined as the I
designer when the LP3907 is powered using a battery.
Note 15: Pins 24, 19 can operate from V
to use a lower voltage rating if the input voltage comes from a buck output.
Note 16: The I
Note 17: VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and
is also different from the nPOR function, which signals if the regulators are in a specified range.
Note 18: Buck V
Symbol
Symbol
IN
IN
, C
minimum for line regulation values is 1.8V.
OUT
Q
Q
Parameter
nPOR = Power on reset forBuck1 and
Buck2
Percentage of Target voltage Buck1 or
Buck2
Output Level Low
can be defined as the standing current of the LP3907 when the I
exhibits a higher current draw when the EN pin is de-asserted because the I
IN
: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
≥
A-MAX
V
OUT
= T
+ 1V.
J-MAX-OP
Input High Level
Input Low Level
2
C bus active, and the other power blocks are active under no load condition. These two values can be used by the system
Parameter
− (θ
IN
JA
min of 1.74 to a V
A-MAX
D-MAX
× P
) is dependent on the maximum operating junction temperature (T
D-MAX
), and the junction-to-ambient thermal resistance of the part/package in the application (θ
). See Applications section.
IN
max of 5.5V. This rating is only for the series pass PMOS power FET. It allows the system design
Default
V
V
Load = IoL = 500mA
BUCK1
BUCK1
AND V
OR V
11
2
Conditions
C bus is active and all other power blocks have been disabled via the I
Conditions
BUCK2
J
BUCK2
= 0°C to +125°C.
falling
2
rising
2 buffer pins draw an additional 2µA.
J
= 25°C. Limits appearing in boldface
(Note
J-MAX-OP
Min
13)
Min
1.2
J
OUT
= 125°C), the maximum power
= 160°C (typ.) and disengages at T
.
Limit
0.23
Typ
50
94
85
Max
0.4
JA
Max
), as given by the
0.5
www.national.com
Units
Units
V
V
2
ms
%
C
V
J