LP3907QTLX-VXSS/NOPB National Semiconductor, LP3907QTLX-VXSS/NOPB Datasheet - Page 25

• Manufacturer Part Number: LP3907QTLX-VXSS/NOPB
• Description: IC REG BUCK SYNC-2 LDO-2 25MSMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3907QTLX-VXSS/NOPB

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 2.1MHz
• Voltage/current - Output 1: 1.8V, 1A
• Voltage/current - Output 2: 3.3V, 600mA
• Voltage/current - Output 3: 2.8V, 300mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 2.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 25-UFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Flexible Power-On Reset (i.e., Power
Good with delay)
The LP3907 is equipped with an internal Power-On-Reset
(“POR”) circuit which monitors the output voltage levels on
bucks 1 and 2. The nPOR is an open drain logic output which
The above diagram shows the simplest application of the
Power On Reset, where both switcher enables are tied to-
gether. In Case 1, EN1 causes nPOR to transition LOW and
triggers the nPOR delay counter. If the power supply for
Buck2 does not come on within that period, nPOR will stay
LOW, indicating a power fail mode. Case 2 indicates the vice
NPOR With Counter Delay
25
is logic LOW when either of the buck outputs are below 91%
of the rising value , or when one or both outputs fall below
82% of the desired value. The time delay between output
voltage level and nPOR is enabled is (50µs, 50ms, 100ms,
200ms) 50ms by default. The system designer can choose
the external pull-up resistor (i.e. 100kΩ) for the nPOR pin.
versa scenario if Buck1 supply did not come on. In both cases
the nPOR remains LOW.
Case 3 shows a typical application of the Power On Reset,
where both switcher enables are tied together. Even if RDY1
ramps up slightly faster than RDY2 (or vice versa), then nPOR
signal will trigger a programmable delay before going HIGH,
as explained below.
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