DSPIC30F5015-20I/PT Microchip Technology, DSPIC30F5015-20I/PT Datasheet - Page 149

• Manufacturer Part Number: DSPIC30F5015-20I/PT
• Description: Digital Signal Processor
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501520IPT

TABLE 20-7:
TABLE 20-8:
RCON
OSCCON 0742
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR
FGS
FICD
Legend:
Note
Name
File Name
SFR
1:
1:
2:
— = unimplemented bit, read as ‘0’
Addr.
— = unimplemented bit, read as ‘0’
0740 TRAPR IOPUWR BGST
0744
0770
0772
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
F8000C
F80000
F80002
F80004
F8000A
Addr.
Bit 15
T5MD
—
—
—
SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F5015/5016
DEVICE CONFIGURATION REGISTER MAP
Bits 23-16
Bit 14
T4MD
—
—
—
—
—
—
—
COSC<2:0>
Bit 13
T3MD
—
—
FWDTEN
MCLREN
Bit 15
FCKSM<1:0>
—
—
Bit 12
T2MD
—
—
—
Bit 14
IC4MD IC3MD
Bit 11
T1MD QEIMD PWMMD
—
—
—
—
—
—
—
Bit 10
Bit 13
—
—
—
—
—
—
—
NOSC<2:0>
IC2MD
Bit 9
Bit 12
—
—
—
—
—
—
—
IC1MD
Bit 8
—
—
—
Bit 11
(1)
—
—
—
—
—
I2CMD
EXTR
Bit 7
—
—
POST<1:0>
PWMPIN
Bit 10
—
—
—
U2MD
SWR
Bit 6
—
—
FOS<2:0>
HPOL
Bit 9
—
—
—
SWDTEN
LOCK
U1MD
Bit 5
—
—
LPOL
Bit 8
(1)
—
—
—
SPI2MD SPI1MD
WDTO
Bit 4
—
—
BOREN
BKBUG
Bit 7
—
—
—
OC4MD OC3MD
SLEEP
Bit 3
CF
Bit 6
COE
—
—
—
—
TUN<4:0>
IDLE
Bit 2
—
—
Bit 5
FWPSA<1:0>
—
BORV<1:0>
—
—
LPOSCEN OSWEN Depends on Configuration bits.
OC2MD
C1MD
Bit 1
BOR
Bit 4
—
—
ADCMD
OC1MD
Bit 0
POR
Bit 3
—
—
—
Reserved
Depends on type of Reset.
FPR<4:0>
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Bit 2
FWPSB<3:0>
—
—
(2)
Reset State
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0