DSPIC30F5015-20I/PT Microchip Technology, DSPIC30F5015-20I/PT Datasheet - Page 65

• Manufacturer Part Number: DSPIC30F5015-20I/PT
• Description: Digital Signal Processor
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501520IPT

8.3
The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a
change-of-state on selected input pins. This module is
capable of detecting input change-of-states, even in
TABLE 8-3:
TABLE 8-4:
TABLE 8-5:
TABLE 8-6:
© 2008 Microchip Technology Inc.
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
Note
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
Note
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
Note
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
Note
Name
Name
Name
Name
SFR
SFR
SFR
SFR
1:
1:
1:
1:
Input Change Notification Module
— = unimplemented bit, read as ‘0’
— = unimplemented bit, read as ‘0’
— = unimplemented bit, read as ‘0’
— = unimplemented bit, read as ‘0’
Addr.
Addr.
00C0
00C2
00C4
00C6
00C0
00C2
00C4
00C6
Addr.
Addr.
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
00C0
00C2
00C4
00C6
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
00C0
00C2
00C4
00C6
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8) FOR dsPIC30F5015
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F5015
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8) FOR dsPIC30F5016
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F5016
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
CN15IE
CN7PUE
CN15IE
CN7PUE
Bit 15
Bit 15
CN7IE
CN7IE
Bit 7
Bit 7
—
—
—
—
—
—
—
—
CN6PUE
CN6PUE
CN14IE
CN14IE
Bit 14
Bit 14
CN6IE
CN6IE
Bit 6
Bit 6
—
—
—
—
—
—
—
—
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
CN5PUE
CN5PUE
CN13IE
CN13IE
CN21IE
Bit 13
CN5IE
Bit 13
CN5IE
Bit 5
Bit 5
—
—
—
—
—
—
CN4PUE
CN4PUE
CN12IE
CN12IE
CN20IE
CN4IE
CN4IE
Bit 12
Bit 12
Bit 4
Bit 4
—
—
—
—
—
—
CN3PUE
CN3PUE
CN19IE
CN11IE
CN11IE
CN3IE
CN3IE
Bit 11
Bit 11
Bit 3
Bit 3
—
—
—
—
—
—
Sleep mode when the clocks are disabled. There are
22 external signals (CN0 through CN21) that may be
selected (enabled) for generating an interrupt request
on a change-of-state.
Please refer to the pin diagrams for CN pin locations.
dsPIC30F5015/5016
CN18PUE CN17PUE CN16PUE
CN2PUE
CN2PUE
CN10IE
CN18IE
CN10IE
CN18IE
CN2IE
CN2IE
Bit 10
Bit 10
Bit 2
Bit 2
—
—
—
—
CN9PUE
CN1PUE
CN9PUE
CN1PUE
CN17IE
CN17IE
CN1IE
CN1IE
CN9IE
CN9IE
Bit 9
Bit 1
Bit 9
Bit 1
—
—
—
—
CN8PUE
CN0PUE
CN8PUE
CN0PUE
CN16IE
CN16IE
CN8IE
CN0IE
CN8IE
CN0IE
Bit 8
Bit 0
Bit 8
Bit 0
—
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
DS70149D-page 65
Reset State
Reset State
Reset State
Reset State
(1)
(1)
(1)
(1)