DSPIC30F5015-20I/PT Microchip Technology, DSPIC30F5015-20I/PT Datasheet - Page 45

• Manufacturer Part Number: DSPIC30F5015-20I/PT
• Description: Digital Signal Processor
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501520IPT

5.2
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The
processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory
location, immediately followed by the address target for
the GOTO instruction. The processor executes the GOTO
to the specified address and then begins operation at
the specified target (start) address.
5.2.1
There are 6 sources of error which will cause a device
Reset.
• Watchdog Time-out:
• Uninitialized W Register Trap:
• Illegal Instruction Trap:
• Brown-out Reset (BOR):
• Trap Lockout:
© 2008 Microchip Technology Inc.
The Watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
Reset Sequence
RESET SOURCES
5.3
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority, as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note that many of these trap conditions can only be
detected
questionable instruction is allowed to complete prior to
trap exception processing. If the user chooses to
recover from the error, the result of the erroneous
action that caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which means that IPL3 is always set
during processing of a trap.
If the user is not currently executing a trap, and sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
The following traps are provided with increasing
priority. However, since all traps can be nested, priority
has little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
• Should an attempt be made to divide by zero, the
• If enabled, a math error trap will be taken when an
• If enabled, a math error trap will be taken when an
• If the shift amount specified in a shift instruction is
Note:
divide operation will be aborted on a cycle
boundary and the trap taken.
arithmetic operation on either Accumulator A or B
causes an overflow from bit 31 and the
Accumulator Guard bits are not utilized.
arithmetic operation on either Accumulator A or B
causes a catastrophic overflow from bit 39 and all
saturation is disabled.
greater than the maximum allowed shift amount, a
trap will occur.
dsPIC30F5015/5016
Traps
when
If the user does not intend to take correc-
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
TRAP SOURCES
they
occur.
Consequently,
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