DSPIC30F5015-20I/PT Microchip Technology, DSPIC30F5015-20I/PT Datasheet - Page 87

• Manufacturer Part Number: DSPIC30F5015-20I/PT
• Description: Digital Signal Processor
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501520IPT

13.4.2
The PWM period is specified by writing to the PRx
register. The PWM period can be calculated using
Equation 13-1.
EQUATION 13-1:
PWM frequency is defined as 1/[PWM period].
FIGURE 13-1:
13.5
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high.
Likewise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
13.6
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic ‘0’.
© 2008 Microchip Technology Inc.
PWM Period = [(PRx) + 1] • 4 • T
Output Compare Operation During
CPU Sleep Mode
Output Compare Operation During
CPU Idle Mode
PWM PERIOD
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
T3IF = 1
PWM PERIOD
(TMRx Prescale Value)
PWM OUTPUT TIMING
Duty Cycle
TMR3 = Duty Cycle (OCxR)
OSC
Period
•
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
T3IF = 1
When the selected TMRx is equal to its respective
Period register, PRx, the following four events occur on
the next increment cycle:
• TMRx is cleared.
• The OCx pin is set.
• The PWM duty cycle is latched from OCxRS into
• The corresponding timer interrupt flag is set.
See Figure 13-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
13.7
The output compare channels have the ability to
generate an interrupt on a compare match, for
whichever match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
Status register and must be cleared in software. The
interrupt is enabled via the respective Compare
Interrupt
corresponding IEC Control register.
For the PWM mode, when an event occurs, the
respective Timer Interrupt Flag (T2IF or T3IF) is
asserted and an interrupt will be generated, if enabled.
The IF bit is located in the IFS0 Status register and
must be cleared in software. The interrupt is enabled
via the respective Timer Interrupt Enable bit (T2IE or
T3IE), located in the IEC0 Control register. The output
compare interrupt flag is never set during the PWM
mode of operation.
TMR3 = Duty Cycle (OCxR)
- Exception 1: If PWM duty cycle is 0x0000,
- Exception 2: If duty cycle is greater than PRx,
OCxR.
dsPIC30F5015/5016
the OCx pin will remain low.
the pin will remain high.
Output Compare Interrupts
Enable
(OCxIE)
bit,
DS70149D-page 87
located
in
the