EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 10
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 10 of 824
- Download datasheet (13Mb)
EP93xx User’s Guide
Chapter 15. UART2 .............................................................................................. 15-1
Chapter 16. UART3 With HDLC Encoder........................................................... 16-1
x
14.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-17
14.3 Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8
14.4 HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8
14.5 UART1 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
15.2 IrDA SIR Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
15.3 UART2 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5
15.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
16.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
16.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3
14.2.2 UART Operation ..........................................................................................................14-5
14.2.3 Interrupts .....................................................................................................................14-7
14.4.1 Overview of HDLC Modes ...........................................................................................14-9
14.4.2 Selecting HDLC Modes ...............................................................................................14-9
14.4.3 HDLC Transmit..........................................................................................................14-11
14.4.4 HDLC Receive...........................................................................................................14-11
14.4.5 CRCs .........................................................................................................................14-12
14.4.6 Address Matching......................................................................................................14-12
14.4.7 Aborts ........................................................................................................................14-13
14.4.8 DMA...........................................................................................................................14-14
14.4.9 Writing Configuration Registers.................................................................................14-14
14.5.1 Clocking Requirements .............................................................................................14-15
14.5.2 Bus Bandwidth Requirements ...................................................................................14-16
15.2.1 IrDA SIR Encoder/decoder Functional Description .....................................................15-1
15.2.2 IrDA SIR Operation......................................................................................................15-3
15.2.3 IrDA Data Modulation ..................................................................................................15-4
15.2.4 Enabling Infrared (Ir) Modes........................................................................................15-5
15.3.1 Clocking Requirements ...............................................................................................15-5
15.3.2 Bus Bandwidth Requirements .....................................................................................15-6
16.2.1 UART3 Package Dependency.....................................................................................16-1
16.2.2 Clocking Requirements ...............................................................................................16-2
16.2.3 Bus Bandwidth Requirements .....................................................................................16-2
14.2.1.9 Interrupt Generation Logic .........................................................................14-4
14.2.1.10 Synchronizing Registers and Logic .........................................................14-5
14.2.2.1 Error Bits....................................................................................................14-6
14.2.2.2 Disabling the FIFOs ...................................................................................14-6
14.2.2.3 System/diagnostic Loopback Testing ........................................................14-6
14.2.2.4 UART Character Frame.............................................................................14-6
14.2.3.1 UARTMSINTR ...........................................................................................14-7
14.2.3.2 UARTRXINTR............................................................................................14-7
14.2.3.3 UARTTXINTR ............................................................................................14-7
14.2.3.4 UARTRTINTR............................................................................................14-8
14.2.3.5 UARTINTR.................................................................................................14-8
15.2.1.1 IrDA SIR Transmit Encoder .......................................................................15-2
15.2.1.2 IrDA SIR Receive Decoder ........................................................................15-2
15.2.2.1 System/diagnostic Loopback Testing ........................................................15-4
©
Copyright 2007 Cirrus Logic, Inc.
DS785UM1
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