EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 106

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

3
3-36
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.5.6 Compare Instructions
31:28
31:28
cond
cond
31:28
cond
Definition:
Mnemonic:
Bit Definitions:
Definition:
Mnemonic:
Bit Definitions:
Definition:
1 1 1 0
1 1 1 0
27:24
27:24
1 1 1 0
27:24
Shift 32-bit Integer Immediate
Shift 64-bit Integer Immediate
Compare Single Precision Floating Point
Shift a 32-bit integer by the count specified in the seven bit, two’s complement
immediate value. A positive number indicates a left shift and a negative
number indicates a right shift. This instruction may also be used to copy a 32-
bit integer from one register to another using a shift value of 0.
CFSH32<cond> CRd, CRn, Shift[6:0]
CRd:
CRn:
Shift[6:0]:
Shifts a 64-bit integer by a count specifies in the seven bit, two’s complement
immediate value. A positive number indicates a left shift and a negative
number indicates a right shift. This instruction may also be used to copy a 64-
bit integer from one register to another by using a shift value of 0.
CFSH64<cond> CRd, CRn, Shift[6:0]
CRd:
CRn:
Shift[6:0]:
Compares two single precision floating point numbers and stores an integer
representing the result in the ARM920T register; the highest four bits of the
integer result match the N, Z, C, and V bits, respectively, in the ARM920T’s
program status register, while the bottom 28 bits are zeros. If Rd = 15, then the
four status bits are stored in the ARM status register, CPSR.
23:22
23:22
0 0
0 0
23:22
0 0
21:20
21:20
0 0
1 0
21
0
Copyright 2007 Cirrus Logic
20
19:16
19:16
1
Destination register
Source register
Shift count.
Destination register
Source register
Shift count.
CRn
CRn
19:16
CRn
15:12
15:12
CRd
CRd
15:12
Rd
0 1 0 1
0 1 0 1
11:8
11:8
0 1 0 0
11:8
Shift[6:4]
Shift[6:4]
7:5
7:5
1 0 0
7:5
4
0
4
0
4
1
Shift[3:0]
Shift[3:0]
DS785UM1
3:0
3:0
CRm
3:0