EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 709

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

AC97GCR
DS785UM1
31
15
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
End Of Interrupt Register. The AC’97 End Of Interrupt Register is a write-only
register that allows the CODECREADY and WIS interrupts to be cleared. A
write to this location clears the interrupt.
RSVD:
CODECREADY:
WINT:
0x8088_009C - Read/Write
Global Control Register. The AC97GCR register is the main control register for
the AC’97 Controller. All bits are cleared on reset.
The AC97IFE creates the clock enable signal for the clock controller block. It
is used to enable/disable both PCLK and AC97LK.
RSVD:
OCODECReady: If set to “1”, this bit will override normal CODEC-ready
LOOP:
AC97IFE:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
CODECREADY Interrupt Status Clear. A write of “1” to this
location will clear the CODECREADY interrupt bit.
Wake-up Interrupt Status Clear. A write of “1” to this
location will clear the WIS interrupt bit.
Reserved. Unknown During Read.
Loopback mode: If this is set to “1”, loopback test mode is
AC97IF Enable: If this bit is set the AC’97 is enabled.
24
8
definition.
enabled. Defaults to “0” when reset. Ensure this bit
is always “0” for normal operation.
Defaults to “0” on reset. When set to “0”, all FIFOs
are reset to “0”.
RSVD
23
7
22
6
21
5
20
4
19
3
OCODECReady
EP93xx User’s Guide
18
2
AC’97 Controller
LOOP
17
1
AC97IFE
22-21
16
0
22