EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 74
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 74 of 824
- Download datasheet (13Mb)
3
3-4
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.1.5 Integer Saturation Arithmetic
A double precision value requires all 64 bits:
A 32-bit integer is stored in the lower 32 bits of a 64-bit register and sign-extended when
written, provided the UI bit in the DSPSC is clear:
Hence, 32-bit integers may be used directly in calculations with 64-bit integers, which are
stored as:
By default, the co-processor treats all 32-bit and 64-bit integers as signed values and
automatically saturates the results of most integer operations and all conversions from
floating-point to integer format. Instructions that may saturate their results are:
This behavior, however, can be altered by setting the UI bit and the ISAT bit in the DSPSC.
With the UI bit clear (the default), 32-bit and 64-bit integer operations are treated as signed
with respect to overflow and underflow detection and saturation as well as compare
operations. Setting the UI bit causes the MaverickCrunch co-processor to treat all 32-bit and
64-bit integer operations as unsigned with respect to overflow, underflow, saturation, and
comparison.
• CFADD32 and CFADD64
• CFSUB32 and CFSUB64
• CFMUL32 and CFMUL64
• CFMAC32 and CFMSC32
• CFCVTS32 and CFCVTD32
• CFTRUNCS32 and CFTRUNCD32
Opcode
Opcode
Opcode
Sign
63
Sign
63
63
62
62
Exponent
Sign Extension
Copyright 2007 Cirrus Logic
52 51
32 31
Data
Sign
Significand
30
Data
DS785UM1
0
0
0
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