EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 616

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

17
17-20
IrDA
EP93xx User’s Guide
17.5.3 IrDA Connectivity
When unexpected frame termination is selected and an underrun occurs, the transmit logic
outputs an abort and interrupts the CPU. An abort continues to be transmitted until data is
once again available in the transmit buffer. The FIR then transmits 16 preambles, a start flag
and starts the new frame. The remote receiver may choose to ignore the abort and continue
to receive data, or to signal the FIR to retry transmission of the aborted frame.
At the end of each frame transmitted, the FIR outputs a pulse called the serial infrared
interaction pulse (SIP). A SIP is required at least every 500 ms to keep slower speed devices
(115.2 kbps and slower) from colliding with the higher speed transmission. The SIP simulates
a start bit which causes all low speed devices to stay off the bus for at least another 500 ms.
Transmission of the SIP pulse causes the transmit pin to be forced high for a duration of
1.625 μs and low for 7.375 μs (total SIP period = 9.0 μs). After the 9.0 μs elapses, the
preamble is then transmitted continuously to indicate to the remote receiver that the FIR’s
transmitter is in the idle state. The preamble continues to be transmitted until new data is
available within the transmit buffer, or the FIR’s transmitter is disabled. Note that it is the
responsibility of the user to ensure that a frame completes once every 500 ms such that a
SIP pulse is produced keeping all low speed devices from interrupting transmission. Because
most IrDA compatible devices produce a SIP after each frame transmitted, the user may only
need to ensure that a frame is either transmitted or received by the FIR every 500 ms.
Note that frame length does not represent a significant portion of the 500 ms time frame in
which a SIP must be produced. At 4.0 Mbps, the longest frame allowed is 16,568 bits, which
takes just over 4 ms to transmit. Also note that the FIR issues a SIP when the transmitter is
first enabled, to ensure all low speed devices are silenced before transmitting its first frame.
If the user disables the FIR’s transmitter during operation, transmission of the current data
byte is stopped immediately, the serial shifter and transmit buffer are cleared. All clocks used
by the transmit logic are automatically shut off to conserve power.
The IrDA controller uses package pins RXD1 and TXD1. The IrDA input signal is always
RXD1. Syscon register DeviceCfg.IonU2 controls what drives bit TXD1. See
Therefore, to use any IrDA mode, FIR, MIR or SIR, set IonU2. To use UART2 as a UART,
clear IonU2.
DeviceCfg.IonU2
0
1
Table 17-4. DeviceCfg.IonU2 Pin Function
UART2 is the output signal
Logical OR of IrDA output signal and UART2 SIR output signal
Copyright 2007 Cirrus Logic
Pin TXD1 Function
Figure
DS785UM1
17-4.