EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 537

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
14.5.1 Clocking Requirements
The use of EGPIO[3] is determined by several bits in Syscon register DeviceCfg. See
Table
There are two clocks, PCLK and UARTCLK.
UARTCLK frequency must accommodate the desired range of baud rates:
The frequency of UARTCLK must also be within the required error limits for all baud rates to
be used.
To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less
than or equal to four times the frequency of PCLK:
EGPIO[0]
EGPIO[3]
HC3EN
14-5.
bit 14
RXD0
TXD0
CTSn
DSRn
DTRn
RTSn
PIN
0
0
x
UART1 input pin
UART1 output pin
Modem input: Clear To Send
Modem input: Data Set Ready (also used for DCDn Data Carrier Detect)
Modem input RIn: Ring Indicator if Syscon register DeviceCfg[25] MODonGPIO is set.
Otherwise, RIn is driven low.
Modem output Data Terminal Ready if Syscon register TESTCR[27] RTConGPIO is clear.
Modem output: Ready To Send
HDLC clock
HC1IN
bit 13
0
1
0
F
UARTCLK
Table 14-5. DeviceCfg Register Bit Functions
HC1EN
F
bit 12
UARTCLK
Table 14-4. UART1 Pin Functionality
x
1
1
Copyright 2007 Cirrus Logic
F
MAX
UARTCLK
≤
MIN
32
≥
External HDLC clock input is driven by EGPIO[3].
×
32 baudrate
Internal HDLC clock output drives EGPIO[3].
65536 b
≤
Description
External HDLC clock input is driven low.
×
4
×
F
× audrate
PCLK
UART1 With HDLC and Modem Control Signals
Function
MAX
MIN
EP93xx User’s Guide
14-15
14