EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 606

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

17
17-10
17.4.1.2.1 Address Field
17.4.1.2.2 Control Field
17.4.1.2.3 Data Field
17.4.1.2.4 CRC Field
IrDA
EP93xx User’s Guide
The 8 bit address field is used by a transmitter to target a select group of receivers when
multiple stations are connected using the infrared link. The address allows up to 255 stations
to be uniquely addressed (00000000b to 11111110b). The global address (11111111b) is used
to broadcast messages to all stations. The serial port contains an 8 bit register that is used to
program a unique address for broadcast recognition as well as a control bit to enable/disable
the address match function. Note that the address of received frames is stored in the receive
buffer along with normal data and that it is transmitted and received starting with its LSB and
ending with its MSB.
The MIR control field is typically 8 bits, but can be any length. The serial port does not provide
any hardware decode support for the control byte, but instead treats all bytes between the
address and the CRC as data. Thus any control bits appear as data to the programmer. Note
that the control field is transmitted and received starting with its LSB and ending with its MSB.
The data field can be any length that is a multiple of 8 bits, including zero. The user
determines the data field length according to the application requirements and transmission
characteristics of the target system. Usually a length is selected which maximizes the amount
of data that can be transmitted per frame, while allowing the CRC checker to be able to
consistently detect all errors during transmission. All data fields must be a multiple of 8 bits. If
a data field that is not a multiple of 8 bits is received, an abort is signalled and the end of
frame tag is set within the receive buffer. Also note that each byte within the data field is
transmitted and received starting with its LSB and ending with its MSB.
MIR uses the established CCITT cyclical redundancy check (CRC) to detect bit errors that
occur during transmission. A 16 bit CRC-CCITT is computed using the address, control and
data fields and is included in each frame. A separate CRC generator is implemented in both
the transmit and receive logic. The transmitter calculates a CRC while data is actively
transmitted and places the 16 bit value at the end of each frame before the stop flag is
transmitted. The receiver calculates a CRC for each received data frame and compares the
calculated CRC to the expected CRC value contained within the end of each received frame.
If the calculated value does not match the expected value, an interrupt is signalled. The CRC
computation logic is preset to all ones before reception/transmission of each frame. Note that
the CRC is transmitted and received starting with its MSB and ending with its LSB. The CRC
uses the four term polynomial:
Copyright 2007 Cirrus Logic
CRC(x) = (x
16
+ x
12
+ x
5
+ 1)
DS785UM1