EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 144

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

5
STFClr
ClkSet1
5-18
System Controller
EP93xx User’s Guide
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
Note: When a write is performed to the ClkSet1 location, it must be immediately followed by 5
Note: The value in the register is the actual coefficient minus one.
30
14
30
14
RSVD
PLL1 X1FBD1
29
13
29
13
NOP instructions. This is needed to flush the instruction pipeline in the ARM920T core.
Writing to this register will cause the the device to enter Standby for between 8 ms to
16 ms. Reading from this register will not cause an entry into Standby mode.
28
12
28
12
0x8093_001C - Write
Writing to the STFClr location will clear the CLDFLG, WDTFLG and RSTFLG
in the register,
the clearing.
RSVD:
0x8093_0020 - Read/Write
The ClkSet1 system control register is one of two register that control clock
speeds.
RSVD:
PLL1_X2IPD:
27
27
11
11
FCLK DIV
26
10
26
10
“PwrSts” on page
Copyright 2007 Cirrus Logic
25
25
9
9
There are no readable bits in this register.
Reserved. Unknown During Read.
These 5 register bits set the input divider for PLL1
operation. On power-on-reset the value is set to 00111b (7
decimal).
SMC ROM
24
8
PLL1 X2FBD2
24
8
RSVD
RSVD
23
nBYP1
7
23
7
5-14. Any data written to the register triggers
22
6
22
6
HCLK DIV
21
5
21
5
20
4
20
4
19
3
19
3
PCLK DIV
PLL1 X2IPD
18
2
18
2
17
1
17
DS785UM1
1
PLL1_PS
16
0
16
0