EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 519

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
Definition:
Bit Descriptions:
The four device configuration registers, SDRAMDevCfg[3:0], specify the
characteristics of the external synchronous memory device types that are
attached to each of the four Synchronous Memory Domains. Only one device
type, SDRAM, SyncROM, or SyncFLASH, can be attached to a given domain,
but the other domains can have different device types attached.
For correct operation, the values written to these configuration registers must
correspond with the values that are programmed into the Mode register that is
inside an SDRAM or SyncROM device.
Changes written to these configuration registers are applied only when the
Synchronous Memory controller is idle or when it becomes idle. This assures
that the Synchronous Memory controller remains synchronized to the state of
the respective synchronous memory device. To assure correct programming
results, these registers should only be written when interrupts, and DMA
operations, are disabled.
RSVD:
AutoPrecharge:
RasToCas:
WBM:
Copyright 2007 Cirrus Logic
Reserved - Unknown During Read
SDRAM Automatic Precharge - Read/Write
During SDRAM initialization, the value written to this bit
specifies if the Synchronous Memory controller should
issue an automatic precharge access to the SDRAM
device, or not:
0 - No automatic precharge access
1 - Issue automatic precharge access
Synchronous memory RAS-to-CAS latency - Read/Write
The value written to this field specifies the RAS-to-CAS
latency that the Synchronous Memory controller uses for
Read or Write accesses to SDRAM or SyncROM devices:
00 - Reserved
01 - Reserved
10 - RAS Latency = 2 (also default value used when
booting from a SyncROM device)
11 - RAS Latency = 3
When performing a Write access, the Synchronous
Memory controller automatically adds one SDCLK cycle to
the RasToCas value. When performing a Read access,
the Synchronous Memory controller uses the RasToCas
value as it is.
Write Burst Mode - Read/Write
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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