EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 150
EP9315-IBZ
Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IBZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1263
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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- Download datasheet (13Mb)
5
BootModeClr
5-24
System Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
DMA_ENFIQ:
USH_ENIRQ:
USH_ENFIQ:
MAC_ENIRQ:
MAC_ENFIQ:
0x8093_0058 - Write Only
The BootModeClr register is a write-to-clear register. Reset activates the boot
ROM remap function causing the internal boot ROM to map to address zero, if
internal boot is selected. Writing BootModeClr removes the internal ROM
address remap, restoring normal address space.
RSVD:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
When set the arbiter will degrant DMA from the AHB bus
and will ignore subsequent requests from DMA if an FIQ is
active. When FIQ is cleared the DMA request is allowed
again. There is no impact on other masters. Reset to 0.
When set the arbiter will degrant USB host from the AHB
bus and will ignore subsequent requests from the USB
Host if an IRQ is active. When IRQ is cleared, the USB
Host request is allowed again. There is no impact on other
masters. Reset to 0.
When set the arbiter will degrant USB Host from the AHB
bus and will ignore subsequent requests from USB Host if
an FIQ is active. When FIQ is cleared, the USB Host
request is allowed again. There is no impact on other
masters. Reset to 0.
When set the arbiter will degrant Ethernet MAC from the
AHB bus and will ignore subsequent requests from the
MAC if an IRQ is active. When IRQ is cleared, the MAC
request is allowed again. There is no impact on other
masters. Reset to 0.
When set the arbiter will degrant the Ethernet MAC from
the AHB bus and will ignore subsequent requests from the
MAC if an FIQ is active. When FIQ is cleared, the MAC
request is allowed again. There is no impact on other
masters. Reset to 0.
There are no readable bits in this register.
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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