EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 169
EP9315-IBZ
Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IBZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1263
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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DS785UM1
CLK1HZ
V_SYNC
INT_VIDEO_FIFO Video FIFO Interrupt. See
INT_SSP1RX
INT_SSP1TX
TC3UI
INT_UART1
SSPINTR
INT_UART2
INT_UART3
USHINTR
INT_PME
Copyright 2007 Cirrus Logic
1 Hz clock interrupt. See
With Software
Vertical or Composite Sync/Frame Pulse Interrupt. See
Chapter
Timing and
Analog/LCD Integrated Timing and Interface"
SSP Receive Interrupt. See
Serial
SSP Transmit Interrupt. See
Serial
Timer Counter 3 Underflow Interrupt. This interrupt
becomes active on the next falling edge of the timer
counter 3 clock after the timer counter has under flowed
(reached zero). The interrupt is cleared by writing any
value to the
"Timers".
UART 1 General Interrupt. This interrupt is active if any
UART1 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART1 to
determine the source of the interrupt. All these sources
are individually maskable within UART1. See
“UART1”.
Synchronous Serial Port (SSP) Interrupt. See
"Synchronous Serial
UART 2 General Interrupt. This interrupt is active if any
UART2 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART2 to
determine the source of the interrupt. All these sources
are individually maskable within UART2. See
"UART2".
UART 3 General Interrupt. This interrupt is active if any
UART3 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART3 to
determine the source of the interrupt. All these sources
are individually maskable within UART3. See
"UART3 With HDLC
USB Host Interrupt. See
Controller”.
PME interrupt. See
Port".
Port".
Port".
7,
Interface".
"Raster Engine With Analog/LCD Integrated
“Timer3Clear”
Trim".
Chapter 23 "Synchronous Serial
Encoder".
Port".
Chapter
Chapter
Chapter
register. See
Chapter 23 "Synchronous
Chapter 23 "Synchronous
Vectored Interrupt Controller
11, “USB Host
20,
7,
"Raster Engine With
"Real Time Clock
EP93xx User’s Guide
Chapter
Chapter
Chapter
Chapter
Chapter 23
18,
15,
16,
15,
6-7
6
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