EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 428
EP9315-IBZ
Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IBZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1263
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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10
10-34
DMA Controller
EP93xx User’s Guide
DAH:
SAH:
TM:
ETDP:
DACKP:
DREQP:
Copyright 2007 Cirrus Logic
Destination Address Hold - This bit is used for external
M2P transfers where the external memory destination is a
memory-mapped FIFO-based device (with one address
location) or for internal peripheral transfers (M2P) to the
peripheral’s FIFO buffer.
1 - Hold the destination address throughout the transfer
(do not increment).
0 - Increment the destination address after each transfer in
the transaction.
Source Address Hold - This bit is used for external DMA
transfers where the external memory source is a memory-
mapped FIFO-based device (with one address location) or
for internal register locations.
1 - Hold the source address throughout the transfer (do
not increment).
0 - Increment the source address after each transfer in the
transaction.
Transfer Mode:
00 - Software initiated DMA transfer.
01 - Hardware initiated external DMA transfer, that is,
transfer from memory to external device or to IDE or SSP.
10 - Hardware initiated external DMA transfer, that is,
transfer from external device (or IDE/SSP) to memory.
11 - Not used.
End-of-Transfer/Terminal Count pin Direction & Polarity:
00 - The DEOT/TC pin is programmed as an active low
end-of-transfer input.
01 - The DEOT/TC pin is programmed as an active high
end-of-transfer input.
10 - The DEOT/TC pin is programmed as an active low
terminal count output.
11 - The DEOT/TC pin is programmed as an active high
terminal count output.
DMA Acknowledge pin Polarity:
0 - DACK is active low.
1 - DACK is active high.
DMA Request pin Polarity. These bits must be set before
the channels ENABLE bit is set. Otherwise the reset
value, “00”, will cause the DMA to look for an active low,
level sensitive DREQ.
00 - DREQ is active low, level sensitive.
01 - DREQ is active high, level sensitive.
10 - DREQ is active low, edge sensitive.
11 - DREQ is active high, edge sensitive.
DS785UM1
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