EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 724
EP9315-IBZ
Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IBZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1263
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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23
Respect to SCLKIN in Microwire Mode
23-12
Synchronous Serial Port
EP93xx User’s Guide
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
SSPRXD
SSPTXD
SFRM
SCLK
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge
of SCLKIN after SFRMIN has gone LOW. Masters that drive a free-running SCLKIN must
ensure that the SFRMIN signal has sufficient setup and hold margins with respect to the
rising edge of SCLKIN.
Figure 23-11
rising edge on which the first bit of receive data is to be sampled by the SSP slave, SFRMIN
must have a setup of at least two times the period of SCLKIN on which the SSP operates.
With respect to the SCLKIN rising edge previous to this edge, SFRMIN must have a hold of
at least one SCLKIN period.
S S P R X D
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements
S F R M IN
S C L K IN
LSB
illustrates these setup and hold time requirements. With respect to the SCLKIN
0
Figure 23-10. Microwire Frame Format (Continuous Transfers)
MSB
4 to 16 bits output data
t
clkm ax
Copyright 2007 Cirrus Logic
t
h o ld
= t
0
S S P C L K IN
LSB
MSB
sam p led b y S S P slave
F irst R X d ata b it to b e
M S B
8-bit control
t
setup
= (2t
S S P C L K IN
)
LSB
MSB
DS785UM1
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