EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 272
EP9315-IBZ
Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IBZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1263
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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8
8-8
Graphics Accelerator
EP93xx User’s Guide
8.4.6 Memory Map Access
8.5.1 Word Count
8.5.1.1 Example: 8 BPP mode
8.5 Register Programming
The Graphics Accelerator has access to the entire memory map. Therefore pixel block
function processing is not limited to graphics and video memory. Font storage, bit map
storage, etc. can be stored anywhere in the memory map. To alleviate page miss penalties
for copies between SDRAM memory pages, the Graphics Accelerator uses a 32-entry copy
buffer during block transfers.
Some of the registers used to operate the Graphics Accelerator need extra explanation for
proper usage. There are two sets such registers. They specify Word Count and Pixel
End/Start values.
The
32-bit words minus 1’ that are to be fetched from the SDRAM buffer. If any pixel bit is in a
word. it must be counted as a full word.
If a Block Copy starts at pixel 0 and 7 pixels are to be copied, the
would be loaded with a 0x1 (2 words - 1 word = 0x1) since the 7th pixel resides in word 1 and
the 0th pixel resides in word 0. The pixels fetched are highlighted in
If a Block Copy starts at pixel 0 and 2 pixels are to be copied, the
would be loaded with 0x0 (1 word - 1 word = 0x0). The pixels fetched are highlighted in
Table
“BLKSRCWIDTH”
0x0000 -
Address
0x000C
8-9.
0x00BC
0x00B0
0x00B4
0x00B8
Table 8-7. 24 bpp Unpacked Memory Organization (1 pixel/ 1 word)
31
FF
EE
DD
and
unused
unused
unused
unused
“BLKDESTWIDTH”
CC
Table 8-8. Transfer Example 1
0 31
Copyright 2007 Cirrus Logic
BB
AA
P(4,5)R
P(5,5)R
P(6,5)R
P(7,5)R
99
88
registers must be written with the ‘number of
0 31
77
66
P(4,5)G
P(5,5)G
P(6,5)G
P(7,5)G
55
44
0 31
“BLKSRCWIDTH”
“BLKSRCWIDTH”
33
Table
22
P(4,5)B
P(5,5)B
P(6,5)B
P(7,5)B
8-8.
11
00
0
DS785UM1
register
register
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