Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 10

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Legacy Interface
The Legacy interface allows access to the Core429 internal registers, FIFO, and internal memory. This interface is
synchronous to the clock. The Tx module contains two 8-bit registers. One is used for control function and the other is
used for status.
Table 11 •
Default Mode Operation
In the default mode, the core operates with the following register map.
CPU Address Map
The address bits 0 and 1 are used to create byte indexes.
For an 8-Bit CPU Data Bus:
1 0
Name
data_ready1
fifo_full1
half_full1
data_ready2
fifo_full2
half_full2
transmit_fifo_full
transmit_half_full
rsel
ctrl_n
str_n
entx
txr
pl1_n
pl2_n
en1_n
en2_n
test
dout
data_valid
ARINC 429 Bus Interface
00 – Byte 0
01 – Byte 1
10 – Byte 2
11 – Byte 3
Legacy Interface Signals
In/Out
Type
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
Receiver 1 FIFO full
Receiver 2 FIFO full
Transmit FIFO half full
Receiver data half word selection
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after
transmission and FIFO empty.
Latch enable for word 1 entered from data bus to transmitter FIFO
Latch enable for word 2 entered from data bus to transmitter FIFO. Must follow pl1_n.
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if en1_n is high
Bidirectional data bus
Data is valid when data_valid = 1
Receiver 1 data ready (FIFO not empty) flag
Receiver 1 FIFO half full
Receiver 2 data ready (FIFO not empty) flag
Receiver 2 FIFO half full
Transmit FIFO full
Clock for control word register
Read status register if rsel = 0, read control register if rsel = 1
Enable transmission
Disable transmitter output if high
v5.0
For a 16-Bit CPU Data Bus:
For 32-Bit CPU Data Bus:
The address bits 2 and 3 select the registers within each
Rx or Tx block (see
00 – Lower half word
10 – Upper half word
00 – Word
Description
"Address Map" on page
11).