Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 6

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Figure 4
Figure 4 •
The Rx block is responsible for recovering the clock from
the input serial data and performs serial-to-parallel
conversion and gap/parity check on the incoming data. It
also interfaces with the CPU.
The Rx module contains two 8-bit registers. One is used
for control function and the other is used for status.
Refer to
for detailed descriptions of the control and status
register bits. The CPU interface configures the internal
RAM with the labels, which are used to compare against
the incoming labels from the received ARINC data.
If the label-compare bit in the receive control register is
enabled, then the data which matches its labels with the
stored labels will be stored in the FIFO. If the label-
compare bit in the receive control register is disabled,
then the incoming data will be stored in the FIFO
without comparing against the labels in RAM.
6
ARINC 429 Bus Interface
cpu_dout
cpu_wait
cpu_wen
cpu_add
cpu_ren
cpu_din
clk
gives a functional description of the Rx block.
Table 14 on page 11
Core429 Rx Block Diagram
RxLo
RxHi
CPU I/F
and
Data Sync
and Clock
Recovery
Table 15 on page 11
Bit Counter
Word Gap
Timer
Parity
Check
Control
Logic
Status Reg
Control Reg
v5.0
The core supports reloading label memory using bit 7 of
the Rx control register. Note that when you set bit 7 to
initialize the label memory, the old label content still
exists, but the core keeps track only of the new label and
does not use the old label during label compare.
The FIFO asserts three status signals:
Depending on the FIFO status signals, the CPU will either
read the FIFO before it overflows, or not attempt to read
the FIFO if it is empty. The interrupt signal int_out_rx is
generated when one of the FIFO status signals
(rx_fifo_empty, rx_fifo_half_full, and rx_fifo_full) are
high.
• rx_fifo_empty: FIFO is empty
• rx_fifo_half_full:
• rx_fifo_full: FIFO is full
programmed RX_FIFO_LEVEL
32-Bit Shift
Register
Compare
Label
FIFO
FIFO
is
filled
Label
Memory
up
to
the