Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 7

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Figure 5
Figure 5 •
The Tx module converts the 32-bit parallel data from the
TX FIFO to serial data. It also inserts the parity bit into
the ARINC data when parity is enabled. The CPU
interface is used to fill the FIFO with ARINC data. The TX
FIFO can hold up to 512 ARINC words of data. The
transmission starts as soon as one complete ARINC word
has been stored in the transmit FIFO.
The Tx module contains two 8-bit registers. One is used
for a control function and the other is used for status.
The CPU interface allows the system CPU to access the
control and status registers within the core.
The TX FIFO asserts three status signals:
• tx_fifo_empty: TX FIFO is empty
• tx_fifo_half_full: TX FIFO is filled up to the
• tx_fifo_full: TX FIFO is full
programmed TX_FIFO_LEVEL
gives a functional description of the Tx block.
Core429 Tx Block Diagram
cpu_dout
cpu_wait
cpu_wen
cpu_add
cpu_ren
cpu_din
clk
CPU I/F
FIFO
Load
32-Bit Parallel-
to-Serial Register
Control Reg
Status Reg
v5.0
Control
Logic
Depending on the FIFO status signals, the CPU will either
read the FIFO before it overflows, or not attempt to read
the FIFO if it is empty. The interrupt signal int_out_tx is
generated when one of the FIFO status signals
(tx_fifo_empty, tx_fifo_half_full and tx_fifo_full) are
high.
Legacy Mode
In this mode, there is a legacy interface block that
communicates with the CPU interface. When legacy
mode is enabled, the core supports two receive (Rx)
channels and one transmit (Tx) channel only. This is not
configurable.
Shift
Parity
Generator
Waveform
Shaper
ARINC 429 Bus Interface
RxHi
RxLo
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