Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 17

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available six cycles after cpu_ren
Figure 11 •
Note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. The write is done two cycles after cpu_wen is
Figure 12 •
Clock Requirements
To
requirements, the Core429 clock input must be 1, 10, 16,
or 20 MHz with a tolerance of ± 0.01%.
Core429 Verification
The comprehensive verification simulation testbench
(included with the Netlist and RTL versions of the core)
verifies correct operation of the Core429 macro. The
verification testbench applies several tests to the
Core429 macro, including:
Using the supplied user testbench as a guide, the user
can easily customize the verification of the core by
adding or removing tests.
Testbench
The CPU model sets up Core429 via the CPU interface
and loads the transmit data
• Receive Interface tests
• Transmit Interface tests
• CPU Interface tests
• Legacy Interface tests
• Loopback tests
meet
cpu_add[8:0]
is sampled.
sampled.
cpu_dout
cpu_wait
cpu_ren
the
CPU Interface Label Memory Read Cycle
CPU Interface Label Memory Write Cycle
clk
ARINC
cpu_din[31:0]
cpu_add[8:0]
cpu_wen
cpu_wait
429
clk
.
The transmit data will be
transmission
bit
A DDR
Data
rate
v5.0
sent to the receiver. The CPU model can retrieve the
receive data through the CPU interface and compare it
against the transmitted data.
The core comes with three testbenches: a full verification
testbench that demonstrates full operation in Verilog,
and two user testbenches, one in VHDL and the other in
Verilog.
The user testbenches are intended to simplify core
integration into the target system
consists of the core connections to a CPU model and
loopback logic that connects Tx output to the Rx input.
Figure 13 •
Model
CPU
Write
Testbench Diagram
Core429
CPU I/F
Data
ARINC 429 Bus Interface
Rx I/F0
Rx I/F3
Tx I/F0
Tx I/F3
(Figure
RxH0
RxL0
TxH0
TxL0
Loopback
I/F
RXH3
RxL3
TxH3
TxL3
13). This
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